Methods of forming fine patterns in the fabrication of semiconductor devices

ABSTRACT

In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 12/290,420, filed on Oct. 30, 2008, which claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2008-0057020, filed on Jun. 17, 2008, the contents of which are incorporated herein by reference in their entirety.

BACKGROUND

With the continued emphasis on highly integrated electronic devices, there is an ongoing need for semiconductor memory devices that operate at higher speeds and lower power and that have increased device density. To accomplish this, there is a pressing need to form devices with aggressive scaling of miniaturized device patterns of ever-smaller line widths.

With increased pressure on the design rules, including, for example, structure size and pitch of semiconductor devices, it has become increasingly difficult to form sufficiently fine pitch patterns due to the resolution limitations of conventional photolithography processes that are used to form the patterns. However, such finely dimensioned line and space patterns, known as “L/S patterns” are critical to device design and integration.

Among the various methods proposed to improve the resolution of conventional photolithography processes, one method, known as the self-aligned-reverse patterning method, or SARP method, has enjoyed widespread popularity. In this approach, a first photolithography pattern is applied to an underlying layer to be patterned. The first photolithography deposition applies structures that are at or near the size and pitch resolution limitations of the photolithography system. A spacer layer is deposited on the resulting structures. The spacer layer is anisotropically etched to form spacers at sidewalls of the structures. The resulting dimensions of the spacers can be accurately controlled by controlling the etch parameters. The original structures are removed, and the spacers remain as an etch mask that can be used to pattern the underlying layer, to result in structures that are finer in width and closer in pitch that that attainable by the photolithography system itself.

There are certain limitations, however, that limit the success of this approach. For example, in a case where certain high-density regions of a device are to include high-density patterns having relatively narrower width and tighter pitch, and low-density regions of a device are to include low-density patterns having relatively larger width and are more spaced apart in pitch, the low-density patterns and high-density patterns are patterned at different times, using different processes. For example, the low-density patterns can be patterned using conventional photolithography tooling, and the high-density patterns, on the same device, are patterned using the SARP approach. As a result, misalignment can occur between the low-density patterns and the high-density patterns, as they are patterned at different times. Also, since they are patterned at different times, extra photolithography steps are required, increasing manufacturing costs.

SUMMARY

Embodiments of the present invention are directed to methods of forming semiconductor devices having both fine patterns, or features, in a first region, and broad patterns, or features, in a second region in a manner that addresses the limitations associated with conventional approaches. In particular, the fine features and broad features of a layer to be patterned, or feature layer, can be formed at the same time, eliminating the possibility of their respective misalignment, and simplifying fabrication by reducing the number of photolithography steps required. This results in a more-reliable fabrication process that is more economical for production of the end-device.

In one aspect, a method of forming a semiconductor device comprises: providing a feature layer on a substrate; providing a mask layer on the feature layer; removing a portion of the mask layer in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located; providing a mold mask pattern on the feature layer in the first region and on the mask layer in the second region; providing a spacer layer on the mold mask pattern in the first region and in the second region; performing an etching process to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region; and etching the feature layer using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

In one embodiment, performing an etching process to etch the mask layer in the second region is performed using the mold mask pattern and spacers as an etch mask.

In another embodiment, the semiconductor device is a memory device, wherein the first region is a cell region of the memory device and wherein the second region is peripheral region of the memory device.

In another embodiment, the feature layer comprises a conductive layer on the substrate.

In another embodiment, the feature layer patterns comprise gate patterns of the semiconductor device.

In another embodiment, the feature layer patterns comprise interconnect lines of the semiconductor device.

In another embodiment, the interconnect lines comprise bit lines of the semiconductor device.

In another embodiment, the feature layer pattern comprises a second mask layer pattern used to define regions in the substrate.

In another embodiment, the defined regions are active regions of the substrate.

In another embodiment, providing the mask layer comprises providing a first mask layer on the feature layer and providing a second mask layer on the first mask layer.

In another embodiment, removing a portion of the mask layer in the first region, the mask layer remaining in a second region of the semiconductor device comprises: removing a portion of the second mask layer in the first region, the second mask layer remaining in a second region of the semiconductor device, and the first mask layer remaining in the first and second regions of the semiconductor device; and wherein etching the feature layer further comprises etching the first mask layer in the first region and in the second region.

In another embodiment, providing the first mask layer on the feature layer and providing a second mask layer on the first mask layer comprises sequentially providing first and second sub-mask layers on the feature layer and providing the second mask layer on the second sub-mask layer.

In another embodiment, the method further comprises, following performing an etching process to etch the mask layer in the second region to provide mask layer patterns in the second region: applying a separation mask in the second region, the separation mask exposing at least one mask layer pattern in the second region; and etching the exposed portion of the at least one mask layer pattern in the second region to separate the at least one mask layer pattern into first and second separated mask layer patterns, and wherein etching the feature layer using the mask layer patterns as an etch mask in the second region comprises etching the feature layer using the first and second separated mask layer patterns as an etch mask.

In another aspect, a method of forming a memory system including: a memory controller that generates command and address signals; and a memory module comprising a plurality of memory devices is provided. The memory module receives the command and address signals and in response stores and retrieves data to and from at least one of the memory devices, wherein each memory device comprises: a plurality of addressable memory cells in a cell region of the memory device; and a decoder in a peripheral region of the memory device that receives an address from an external source, and that generates a row signal and a column signal for accessing at least one of the addressable memory cells during programming and read operations. The method further comprises forming the memory device comprising: providing a feature layer on a semiconductor substrate; providing a mask layer on the feature layer; removing a portion of the mask layer in the cell region of the memory device where fine features of the feature layer are to be located, the mask layer remaining in the peripheral region of the memory device where broad features of the feature layer are to be located; providing a mold mask pattern on the feature layer in the cell region and on the mask layer in the peripheral region; providing a spacer layer on the mold mask pattern in the cell region and in the peripheral region; performing an etching process to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the peripheral region to provide mask layer patterns in the peripheral region; and etching the feature layer using the mask layer patterns as an etch mask in the peripheral region and using the spacers as an etch mask in the cell region to provide a feature layer pattern having fine features in the cell region and broad features in the peripheral region.

In one embodiment, performing an etching process to etch the mask layer in the peripheral region is performed using the mold mask pattern and spacers as an etch mask.

In another embodiment, the feature layer comprises a conductive layer on the substrate.

In another embodiment, the feature layer patterns comprise gate patterns of the memory device.

In another embodiment, the feature layer patterns comprise interconnect lines of the memory device.

In another embodiment, the interconnect lines comprise bit lines of the memory device.

In another embodiment, the feature layer pattern comprises a second mask layer pattern used to define regions in the semiconductor substrate.

In another embodiment, the defined regions are active regions of the semiconductor substrate.

In another embodiment, providing the mask layer comprises providing a first mask layer on the feature layer and providing a second mask layer on the first mask layer.

In another embodiment, removing a portion of the mask layer in the cell region, the mask layer remaining in the peripheral region of the semiconductor device comprises: removing a portion of the second mask layer in the cell region, the second mask layer remaining in the peripheral region of the memory device, and the first mask layer remaining in the cell and peripheral regions of the memory device; and wherein etching the feature layer further comprises etching the first mask layer in the cell region and in the peripheral region.

In another embodiment, providing the first mask layer on the feature layer and providing a second mask layer on the first mask layer comprises sequentially providing first and second sub-mask layers on the feature layer and providing the second mask layer on the second sub-mask layer.

In another embodiment, the method further comprises, following performing an etching process to etch the mask layer in the peripheral region to provide mask layer patterns in the peripheral region: applying a separation mask on the peripheral region, the separation mask exposing at least one mask layer pattern in the peripheral region; and etching the exposed portion of the at least one mask layer pattern in the peripheral region to separate the at least one mask layer pattern into first and second separated mask layer patterns, and wherein etching the feature layer using the mask layer patterns as an etch mask in the peripheral region comprises etching the feature layer using the first and second separated mask layer patterns as an etch mask.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of the embodiments of the invention will be apparent from the more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the drawings:

FIG. 1 is a block diagram of a NAND-flash memory device, illustrating an example application of the embodiments the present invention.

FIG. 2 is a schematic diagram of the device of FIG. 1.

FIG. 3 is top layout view of a NAND-flash memory device, formed in accordance with embodiments of the present invention.

FIGS. 4A-14A are top plan views of a method for forming fine patterns and broad patterns in the example NAND-flash memory device of FIG. 3, in accordance with embodiments of the present invention. FIGS. 4B-14B are cross-sectional views taken along section lines A-A′, B-B′, and C-C∝ of FIGS. 4A-14A, in accordance with embodiments of the present invention

FIG. 15 is a block diagram of a memory card that includes a semiconductor device formed in accordance with the embodiments of the present invention.

FIG. 16 is a block diagram of a memory system that employs a memory module, formed in accordance with the embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Like numbers refer to like elements throughout the specification.

It will be understood that, although the terms first, second, etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being “on” or “connected” or “coupled” to another element, it can be directly on or above, or connected or coupled to, the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly on” or “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). When an element is referred to herein as being “over” another element, it can be over or under the other element, and either directly coupled to the other element, or intervening elements may be present, or the elements may be spaced apart by a void or gap.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

FIG. 1 is a block diagram of a NAND-flash memory device, illustrating an example application of the embodiments the present invention. FIG. 2 is a schematic diagram of the device of FIG. 1. Referring to FIGS. 1 and 2, a memory device, such as a NAND-flash memory device includes a memory cell array 100 comprising an array of memory cells arranged in a high-density configuration. Peripheral circuitry for accessing and driving the array includes an X-decoder block 110 responsible for selecting a word line WL of the cell array 100 to be accessed, for example, word lines WL₀-WL_(m). A Y-decoder block 120 is responsible for selecting a bit line BL of the cell array 100 to be activated, for example, bit lines BL₀-BL_(n). A Y-path circuit 130 connected to the cell array 100 is responsible for assigning the bit line path based on the output of the Y-decoder block 120.

Referring to FIG. 2, a cell string 10 of the memory cell array 100 includes a string select transistor 16, a plurality of memory cell transistors 12, and a ground select transistor 14 connected in series. A gate of the string select transistor 16 is connected to the string select line SSL and a gate of the ground select transistor 14 is connected to the ground select line GSL. A gate of each memory cell transistor 12 in the string 16 is connected to one of the word lines WL₀-WL_(m). The memory cell transistors 12 include charge storage structures and thereby operate as non-volatile devices which retain information after power is removed from the device. Bit lines BL₀-BL_(n) of the device are connected between output terminals of string select transistors SSL of a common row.

FIG. 3 is top layout view of the example NAND-flash memory device of FIGS. 1 and 2 above, formed in accordance with embodiments of the present invention. Referring to FIG. 3, a memory device, such as a NAND flash memory, commonly includes a number of different circuit regions, each having circuit structures with certain size and pitch characteristics. For example, the device of FIG. 3 includes a cell array region 300A, a cell contact region 300B and a peripheral circuit region 300C. In one example, the broadly patterned X-decoder and Y-decoder circuitry of FIG. 1 can be formed in the peripheral circuit region 300C of the device, where design constraints are not as stringent. At the same time, the memory cell array 100 can be formed in the memory cell region 300A of the device. In general, the memory cell region 300A has the highest demand for density in the device, and therefore, finely patterned structures are desired in the memory cell region 300A. The cell contact region 300B serves as the interface between the memory cell region 300A and the peripheral circuit region. Therefore, in the cell contact region 300B, it is common to have both finely patterned structures and broadly patterned structures.

For purposes of the present disclosure, the terms “broad”, “broadly”, “wide” and the like when referring to patterning of layers, features, or structures of a device refer to patterns, features, or structures that can be formed using conventional photolithographic techniques and dimensioned or spaced apart from each other by distances that are at least as large as those readily attained under the resolution of the photolithography system. The terms “fine”, “finely”, “narrow” and the like when referring to patterning of layers, features, or structures of a device refer to patterns, features, or structures that cannot be formed using conventional photolithographic techniques and are dimensioned or spaced apart from each other by distances that are less than those readily attained under the resolution of the photolithography system used in their formation. For example, patterns, features, or structures that are “fine” or “narrow” may require the use of sidewall spacers and etching techniques in defining their eventual geometries and spacings.

It can be seen in the highlighted region identified within Box IV, that patterns of various widths are desired to be formed. For example, the conductive lines 301 . . . 332 comprising, for example, conductive lines for bit lines and word lines of the device, are patterns of a fine width W1 and are at a fine pitch. At the same time, the string select line SSL, in parallel with the conductive lines 301 . . . 332, is formed at a much broader width of W2, while the ground select line GSL, likewise in parallel with the conductive lines 301 . . . 332, is formed at a much broader width of W3. Also, in the cell contact region 300B, it can be seen that relatively broadly patterned contacts 352 are required for the relatively narrowly patterned conductive lines 301 . . . 332.

Embodiments of the present invention provide fabrication techniques for forming both narrowly patterned features and broadly patterned features in a manner that mitigates or eliminates the possibility of their respective misalignment, and that simplifies fabrication by reducing the number of photolithography steps required. This results in a more-reliable fabrication process that is more economical for production of the end-device.

FIGS. 4A-14A are top plan views of a method for forming fine patterns and broad patterns in the example NAND-flash memory device of FIG. 3, in accordance with embodiments of the present invention. FIGS. 4B-14B are cross-sectional views taken along section lines A-A′, B-B′, and C-C∝ of FIGS. 4A-14A, in accordance with embodiments of the present invention.

In particular FIGS. 4A-14A and 4B-14B illustrate formation of the patterns illustrated in Box IV of FIG. 3 for illustrating the principles of the embodiments of the present specification.

Referring to FIGS. 4A and 4B, a layer to be patterned 430, or feature layer, is provided on a substrate 400. The layer to be patterned 430 can be formed of any of a number of relevant materials. In one example, the layer to be patterned 430 can comprise an active region, or other region, of the substrate 400 itself, such as a semiconductor substrate 400. In another example, the layer to be patterned can itself comprise a masking layer that is used to define patterns in an underlying substrate or material layer. In this case, the layer to be patterned 430 can be a mask layer used to define regions of the substrate 400. In another example, the layer to be patterned 430 can comprise a conductive layer that is formed on an underlying insulating layer in turn formed on the substrate 400. In another example, the layer to be patterned 430 can comprise a gate electrode of a transistor. In another example, the layer to be patterned 430 can comprise a conductive line of a device, such as a bit line or word line of the device. When forming a gate electrode, the layer to be patterned 430 can comprise, for example, a material selected from the group consisting of TaN, TiN, W, WN, HfN, and WSi, and a combination of two or more of these materials. When forming a bit line, the layer to be patterned 430 can comprise, for example, a metal or metal alloy material, such as tungsten or aluminum. In a case where the layer to be patterned 430 comprises a conductive layer that requires isolation from the underlying substrate 400, and insulative layer (not shown) can be provided between the layer to be patterned 430 and the substrate.

A first hard mask layer 432 is applied to the layer to be patterned 430. An optional second hard mask layer 434 and optional third hard mask layer 440 can be applied to the first hard mask layer 432. In a case where first and second hard mask layers 432, 434 are used, the first and second hard mask layers 432, 434 should have etch selectivity with respect to each other. In a case where first, second, and third hard mask layers 432, 434, 440 are used, the first and third hard mask layers 432, 440 should have etch selectivity with respect to the second hard mask layer 434. Additional hard mask layers can be applied accordingly, as desired.

In various examples, the hard mask layers 432, 434, 440 can comprise any of a number of suitable materials. In one embodiment, the first hard mask layer 432 can comprise oxide, in which case the second hard mask layer 434 can comprise polysilicon or nitride. The third hard mask layer 440 can comprise a material having the same etch selectivity as that of the first hard mask layer 432; therefore, in this example, the third hard mask layer 440 can comprise oxide. Other suitable materials for the hard mask layers 432, 434, 440 are equally applicable to the embodiments of the present specification.

Referring to FIGS. 5A and 5B, the third hard mask layer 440 is patterned to remove the third hard mask layer 440 in regions or portions of the device where fine, or narrow, features of the feature layer, or layer to be patterned 430, are to be located. At the same time, the resulting third hard mask layer pattern 440 a remains in regions or portions of the device where broad features of the feature layer, or layer to be patterned 430, are to be located. In this example, the third hard mask layer pattern 440 a exposes regions of the device where the relatively fine, or narrow, conductive lines 301 . . . 332 are to be formed. At the same time, the third hard mask layer pattern 440 a remains in regions of the device where the relatively broad ground select line GSL and contacts 352 are to be formed. Alternatively, in a case where only one or two hard mask layers are employed, an uppermost hard mask layer of the hard mask layers 432, 434 is patterned as described above.

Referring to FIGS. 6A and 6B, a mold mask pattern 450 is provided on the resulting structure. In particular, the mold mask pattern 450 can include relatively narrow first portions 450(450 s) that, for example, can correspond with the conductive lines 301 . . . 332 to be formed in the portions of the device where fine, or narrow, features of the feature layer, or layer to be patterned 430, are to be located. The first portions 450(450 s) of the mold mask pattern 450 are positioned on the second hard mask layer 434. The mold mask pattern 450 can further include relatively broad second portions 450(450 w) that, for example, can correspond with the ground select line GSL and contacts 352 to be formed in the portions of the device where broad features of the feature layer, or layer to be patterned 430, are to be located. The second portions 450(450 w) of the mold mask pattern 450 are positioned on the remaining portions of the third hard mask layer pattern 440 a. Referring to FIG. 6A, this view shows that in some cases, the first portions 450(450 s) of the mold mask pattern can be connected to the second portions 450(450 w) of the mold mask pattern, whereas, in other cases, they are isolated from each other.

The mold mask layer 450 can comprise, in one embodiment, a carbon-containing layer or a polysilicon layer. In the event a carbon-containing material layer is used, the mold mask layer 450 can comprise a hydrocarbon having an aromatic ring or organic compound comprising its derivative. For example, the mold mask layer material 450 can comprise an organic compound having an aromatic ring, such as phenyl, benzene, or naphthalene. Alternatively, the mold mask layer material 450 can comprise a material having a relatively high carbon level of 85-99 wt % of the organic compound. In one embodiment, the mold mask layer 450 can be applied using a spin-coating process, and can be patterned using conventional photolithography techniques.

Referring to FIGS. 7A and 7B, a conformal spacer layer 460 is applied to the resulting structure, covering a top and sidewalls of the mold mask layer pattern 450. In one embodiment, the spacer layer 460 is formed of a material that has etch selectivity with regard to the material of the mold mask layer 450 and the underlying second hard mask layer 434.

Referring to FIGS. 8A and 8B, the spacer layer 460 is etched to form sidewall spacers 460 a at sidewalls of the mold mask layer pattern elements 450. Referring to FIG. 8A, it can be seen that the resulting sidewall spacers 460 border the perimeter of the original mold mask layer pattern elements 450. Following this, the third hard mask layer pattern 440 a is etched to form third hard mask layer pattern 440 b, using the mold mask layer pattern 450 and the spacers 460 a as an etch mask.

Alternatively, in an embodiment where the spacer layer 460 and the third hard mask layer 440 are the same material, the etching of the spacer layer 460 to form the sidewall spacers 460 a also results in an etching of the third hard mask layer pattern 440 a to form third hard mask layer pattern 440 b. In this case, the etching of the sidewall spacers 460 a and the third hard mask layer pattern 440 b can be performed in a single step.

Referring to FIGS. 9A and 9B, the mold mask layer pattern 450 is selectively removed. As a result the spacer structures 460 a remain. In particular, the spacer structures 460 a can include first spacer structures 460 a that are closely spaced apart at a narrow pitch to correspond with the conductive lines 301 . . . 332 to be formed in the portions of the device where fine, or narrow, features of the feature layer, or layer to be patterned 430, are to be located. The first spacer structures 460 a are positioned on the second hard mask layer 434 in this example. The first spacer structures 460 a can further include second spacer structures 460 a that are relatively more further spaced apart at a broader pitch that, for example, can correspond with the ground select line GSL and contacts 352 to be formed in the portions of the device where broad features of the feature layer, or layer to be patterned 430, are to be located. The second spacer structures 460 a are positioned on the remaining portions of the third hard mask layer pattern 440 b in this example. In a case where the mold mask pattern 450 material comprises a carbon-containing layer, it can be removed by performing an ashing and stripping procedure.

Referring to FIGS. 10A and 10B, a separation mask pattern 470 is applied to the resulting structure. In the present example, the separation mask pattern 470 exposes a portion of the underlying third hard mask layer pattern 440 b. In one embodiment, the separation mask pattern 470 is applied using conventional photolithography techniques.

Referring to FIGS. 11A and 11B, the third hard mask layer pattern 440 b is etched using the separation mask pattern as an etch mask to form third hard mask layer pattern 440 c. In this manner, portions of the third hard mask layer pattern 440 b are separated into independent portions 440 c. In addition, formerly connected portions of the sidewall spacers 460 a are likewise separated into independent portions. In particular, this trimming procedure is applicable to low-density regions of the device, for example, in the cell contact region 300B. In this example, separated portions of the third hard mask layer pattern 440 c in the cell contact region 300B correspond with separated contacts 352 to be formed during subsequent processes.

Referring to FIGS. 12A and 12B, the second hard mask layer 434 is etched using the sidewall spacers 460 a, the third hard mask pattern 440 b and the third hard mask pattern 440 c as an etch mask to form a patterned second hard mask layer 434 a.

Referring to FIGS. 13A and 13B, the first hard mask layer 432 is etched using the patterned second hard mask layer 434 a and any remaining portions of the sidewall spacers 460 a, the third hard mask pattern 440 b and the third hard mask pattern 440 c as an etch mask to form a patterned first hard mask layer 432 a. As a result of this procedure, the feature layer, or layer to be patterned 430 is exposed.

Referring to FIGS. 14A and 14B, the feature layer, or layer to be patterned 430, is etched and patterned using the patterned first hard mask layer 432 a and any remaining portions of the second hard mask layer pattern 434 a as an etch mask to form a patterned feature layer 430. The patterned feature layer 430 in this example, includes fine, or narrow, first features 430 a which operate as conductive lines 301 . . . 332 of the device. The first features 430 a can be of a fine width or fine pitch that is less than a width or pitch that would otherwise be attainable by the resolution of the photolithography system used. For example, the first features 430 a can be one-half of the otherwise attainable width or pitch. In addition, the patterned feature layer 430, includes relatively broad second and third features 430 b, 430 c which operate as the ground select line GSL and contacts 352 of the device.

It will be apparent that the first and second hard mask layers 432, 434 and the steps involved in their subsequent patterning are optional, and not required, depending on the application. Multiple masking layers are desirable in fabrication processes as pattern widths continue to decrease in size. The number of layers and the types of materials used for the mask layers depend on the level of integration and the fabrication process employed.

FIG. 15 is a block diagram of a memory card that includes a semiconductor device in accordance with the embodiments of the present invention. The memory card 1200 includes a memory controller 1220 that generates command and address signals C/A and a memory module 1210 for example, flash memory 1210 that includes one or a plurality of flash memory devices. The memory controller 1220 includes a host interface 1223 that transmits and receives command and address signals to and from a host, a controller 1224, and a memory interface 1225 that in turn transmits and receives the command and address signals to and from the memory module 1210. The host interface 1223, the controller 1224 and memory interface 1225 communicate with controller memory 1221 and processor 1222 via a common bus.

The memory module 1210 receives the command and address signals C/A from the memory controller 1220, and, in response, stores and retrieves data DATA I/O to and from at least one of the memory devices on the memory module 1210. Each memory device includes a plurality of addressable memory cells and a decoder that receives the receives the command and address signals, and that generates a row signal and a column signal for accessing at least one of the addressable memory cells during programming and read operations.

Each of the components of the memory card 1200, including the memory controller 1220, electronics 1221, 1222, 1223, 1224, and 1225 included on the memory controller 1220 and the memory module 1210 can be formed to include fine patterns using processing techniques in accordance with the embodiments disclosed herein.

FIG. 16 is a block diagram of a memory system 1300 that employs a memory module 1310, for example, of the type described herein. The memory system 1300 includes a processor 1330, random access memory 1340, user interface 1350 and modem 1320 that communicate via a common bus 1360. The devices on the bus 1360 transmit signals to and receive signals from the memory card 1310 via the bus 1360. Each of the components of the memory system 1300, including the processor 1330, random access memory 1340, user interface 1350 and modem 1320 along with the memory card 1310 can be formed to include fine patterns using processing techniques in accordance with the embodiments disclosed herein. The memory system 1300 can find application in any of a number of electronic applications, for example, those found in consumer electronic devices such as solid state drives (SSD), CMOS image sensors (CIS) and computer application chip sets.

The memory systems and devices disclosed herein can be packaged in any of a number of device package types, including, but not limited to, ball grid arrays (BGA), chip scale packages (CSP), plastic leaded chip carrier (PLCC) plastic dual in-line package (PDIP), multi-chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stock package (WSP).

While embodiments of the invention have been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims. 

What is claimed is:
 1. A semiconductor device comprising: a substrate; a pair of finely patterned conductive lines formed on the substrate, wherein each of the pair of finely patterned conductive lines has a first portion extending in a first direction and a second portion extending in a second direction, wherein the second direction is perpendicular to the first direction; and a pair of broadly patterned conductive contacts adjacent to ends of the second portions of the pair of finely patterned conductive lines, wherein the pair of broadly patterned conductive contacts have first sidewalls facing each other and second sidewalls opposite to the first sidewalls, respectively, wherein opposite sidewalls of the second portions of the pair of finely patterned conductive lines is are aligned with the second sidewalls of the pair of broadly patterned conductive contacts, wherein the first portion of one of the pair of finely patterned conductive lines is closest to the first portion of the other of the pair of finely patterned conductive lines from among other conductive lines, and wherein the second portion of one of the pair of finely patterned conductive lines and one of the pair of broadly patterned conductive contacts have different widths from each other in the first direction.
 2. The semiconductor device of claim 1, wherein bottom surfaces of the pair of finely patterned conductive lines and the pair of broadly patterned conductive contacts are coplanar.
 3. The semiconductor device of claim 1, wherein a minimum feature size of one of the pair of broadly patterned conductive contacts is greater than a feature size of one of the pair of finely patterned conductive lines, and wherein the pair of finely patterned conductive lines comprise a feature size not readily attainable under the resolution of the photolithography system used in their formation.
 4. The semiconductor device of claim 1, wherein the substrate comprises a cell array region and a cell contact region, wherein the pair of finely patterned conductive lines are is formed in the cell array region and the cell contact region, and wherein the pair of broadly patterned conductive lines are formed in the cell contact region.
 5. The semiconductor device of claim 1, wherein each of the pair of finely patterned conductive lines are electrically connected to each of the pair of broadly patterned conductive contacts, respectively.
 6. The semiconductor device of claim 1, further comprising: another finely patterned conductive line formed on the substrate, the another finely patterned conductive line being in mirror image arrangement with respect to one of the pair of finely patterned conductive lines and being spaced apart from the one of the pair of finely patterned conductive lines; and another broadly patterned conductive contact formed on the substrate, the another broadly patterned conductive contact being in mirror image arrangement with respect to one of the pair of broadly patterned conductive contacts and being spaced apart from the one of the pair of broadly patterned conductive contacts.
 7. A semiconductor device comprising: a substrate; a pair of finely patterned conductive lines formed on the substrate, wherein a first portion of one of the pair of finely patterned conductive lines extends in a first direction and a second portion of one of the pair of finely patterned conductive lines extends in a second direction, wherein the second direction is perpendicular to the first direction, and wherein each finely patterned conductive line of the pair of finely patterned conductive lines is spaced apart with a first width; and a pair of broadly patterned conductive contacts each having first sidewalls facing each other and second sidewalls opposite to the first sidewalls, respectively, wherein one of the pair of broadly patterned conductive contacts is adjacent to an end of the second portion of the one of the pair of finely patterned conductive lines, wherein each broadly patterned conductive contact of the pair of broadly patterned conductive contacts is spaced apart with a second width, wherein the second width is greater than the first width, and wherein opposite sidewalls of the second portions of the pair of finely patterned conductive lines are aligned with the second sidewalls of the pair of broadly patterned conductive contacts, wherein the first portion of one of the pair of finely patterned conductive lines is closest to the first portion of the other of the pair of finely patterned conductive lines from among other conductive lines, and wherein the second portion of the one of the pair of finely patterned conductive lines and the one of the pair of broadly patterned conductive contacts adjacent to the end of the second portion of the one of the pair of finely patterned conductive lines have different widths from each other in the first direction.
 8. The semiconductor device of claim 7, wherein bottom surfaces of the pair of finely patterned conductive lines and the pair of broadly patterned conductive contacts are coplanar.
 9. The semiconductor device of claim 7, wherein the pair of finely patterned conductive lines comprise feature sizes less than those readily attainable under the resolution of the photolithography system used in their formation.
 10. The semiconductor device of claim 7, wherein the first width is less than a width readily attainable under the resolution of the photolithography system used in their formation.
 11. The semiconductor device of claim 7, wherein the substrate comprises a cell array region and a cell contact region, wherein the pair of finely patterned conductive lines is formed in the cell array region and in the cell contact region, and wherein the pair of broadly patterned conductive contacts is formed in the cell contact region.
 12. The semiconductor device of claim 7 further comprising a plurality of pairs of broadly patterned conductive contacts, wherein the plurality of pairs of broadly patterned conductive contacts are arranged in a step-structure formation extending in the first direction, and wherein each pair of broadly patterned conductive contacts is shifted a distance in the second direction relative to its neighboring pairs.
 13. The semiconductor device of claim 7, wherein the one of the pair of broadly patterned conductive contacts is electrically connected to the end of the second portion of the one of the pair of finely patterned conductive lines.
 14. The semiconductor device of claim 7, further comprising: another pair of finely patterned conductive lines formed on the substrate, the another pair of finely patterned conductive lines being in mirror image arrangement with respect to the pair of finely patterned conductive lines and being spaced apart from the pair of finely patterned conductive lines; and another pair of broadly patterned conductive contacts formed on the substrate, the another pair of broadly patterned conductive contacts being in mirror image arrangement with respect to the pair of broadly patterned conductive contacts and being spaced apart from the pair of broadly patterned conductive contacts.
 15. A semiconductor device comprising: a substrate having a cell array region and a cell contact region; a pair of finely patterned conductive lines formed on the substrate, wherein each of the pair of a finely patterned conductive lines has a first portion extending in a first direction in the cell array region and in the contact region, and a second portion extending in a second direction in the cell contact region, and wherein the second direction is perpendicular to the first direction; and a pair of broadly patterned conductive contacts adjacent to ends of the second portions of the pair of finely patterned conductive lines in the cell contact region, wherein one of the of broadly patterned conductive contacts has a minimum feature size greater than a feature size of one of the pair of finely patterned conductive lines, wherein one of the pair of finely patterned conductive lines comprises a feature size not readily attainable under the resolution of the photolithography system used in their formation, wherein the pair of broadly patterned conductive contacts have first sidewalls facing each other and second sidewalls opposite to the first sidewalls, respectively, wherein opposite sidewalls of the second portions of the pair of finely patterned conductive lines extend in the second direction, and wherein the opposite sidewalls of the second portions of the pair of finely patterned conductive lines are collinear with a the second sidewalls of the pair of broadly patterned conductive contacts, wherein the first portion of one of the pair of finely patterned conductive lines is closest to the first portion of the other of the pair of finely patterned conductive lines from among other conductive lines, and wherein the second portion of one of the pair of finely patterned conductive lines and one of the pair of broadly patterned conductive contacts have different widths from each other in the first direction.
 16. The semiconductor device of claim 15, wherein each line of the pair of finely patterned conductive lines is spaced apart with a first width; wherein each contact of the pair of broadly patterned conductive contacts is spaced apart with a second width, wherein the second width is greater than the first width, and wherein opposite sidewalls of the second portions of the pair of finely patterned conductive lines are aligned with the second sidewalls of the pair of broadly patterned conductive contacts.
 17. The semiconductor device of claim 16, wherein the first width is less than those readily attainable under the resolution of the photolithography system used in their formation.
 18. The semiconductor device of claim 15 further comprising a plurality of the pair of broadly patterned conductive contacts, wherein the plurality of pairs of broadly patterned conductive contacts are arranged in a step-structure extending in the first direction, and wherein each pair of broadly patterned conductive contacts is shifted a distance in the second direction relative to its neighboring pairs.
 19. The semiconductor device of claim 15, wherein each of the pair of finely patterned conductive lines are electrically connected to each of the pair of broadly patterned conductive contacts, respectively.
 20. The semiconductor device of claim 15, further comprising: another finely patterned conductive line formed on the substrate, the another finely patterned conductive line being in mirror image arrangement with respect to the pair of finely patterned conductive lines and being spaced apart from the pair of finely patterned conductive lines; and another broadly patterned conductive contact formed on the substrate, the another broadly patterned conductive contact being in mirror image arrangement with respect to the pair of broadly patterned conductive contacts and being spaced apart from the pair of broadly patterned conductive contacts. 